Генератор Verilog для сумматора по модулю 2^n-1
Выберите n для модуля 2
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Комбинационная реализация без мультиплексоров:
// Sum modulo (2^3 - 1) = 7 module sum_modulo_7 (A, B, S); input [2:0] A; input [2:0] B; output[2:0] S; wire [2:0] G; wire [2:0] P; wire [2:0] C; assign G[0] = A[0]&B[0]; assign G[1] = A[1]&B[1]; assign G[2] = A[2]&B[2]; assign P[0] = A[0]^B[0]; assign P[1] = A[1]^B[1]; assign P[2] = A[2]^B[2]; assign C[0] = G[0] | G[2]&P[0] | G[1]&P[0]&P[2]; assign C[1] = G[1] | G[0]&P[1] | G[2]&P[1]&P[0]; assign C[2] = G[2] | G[1]&P[2] | G[0]&P[2]&P[1]; assign S[0] = (P[0]&&(~P[2:0]))^C[2]; assign S[1] = (P[1]&&(~P[2:0]))^C[0]; assign S[2] = (P[2]&&(~P[2:0]))^C[1]; endmodule
Тест-бенч:
module atest_bench(); reg [2:0] in1; reg [2:0] in2; wire [2:0] out; integer i, j, l, m, t; reg dummy; wire complete; integer fori, forj; sum_modulo_7 sm1(in1, in2, out); initial begin for (fori = 0; fori < 7; fori = fori + 1) begin for (forj = 0; forj < 7; forj = forj + 1) begin in1 = fori; in2 = forj; m = (fori + forj) % 7; #1 dummy = 1; $display ("!!! IN1=(%d) IN2=(%d) Res=(%d) Expect=(%d)", fori, forj, out, m); l = out; if (l != m) begin $display ("!!! Error (%d, %d)!!!", l, m); end #1 dummy = 1; end end end endmodule
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