Nadezhda - Reliability Enhancement Logic tool for Integrated Circuits design

Quick overview

Nadezhda - software for increasing the reliability of logic circuits by changing the structure of combination sections at the gate-level verilog netlist.

Detailed description

The fault tolerance of logic circuits is currently attracting increased interest. This is due to a number of objective reasons, including the high importance of microelectronics for fault-critical applications in the field of Space and Industry. Here is a simplified classification of destabilizing effects, as well as a classification of the errors caused by these effects. And here is another one of those objective reasons – it is a rapid increase in the soft error rate in combinational logic compared to other types of errors. It is due to the some technology trends on the soft error rate of combinational logic.

* - T. Yaran, S. Tosun Improving combinational circuit resilience against soft errors via selective resource allocation // 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

There is a large set of methods for designing around SET. In our research we deal with the most influential but probably the most underestimated technique – logic masking. It is believed that Logical masking is technology-independent and has the most impact on the soft error rate (SER) of the circuit.

* - Asadi H, Tahoori MB, Fazeli M, Miremadi SG. Efficient algorithms to accurately compute derating factors of digital circuits. Microelectron Reliab 2012;52(6):1215–26.

Actually, there are three types of Masking:

Logical masking is the most undervalued mechanism, because on the one hand it is technologically independent and has the greatest influence on the final SER, and on the other hand it is not supported by any commercially available EDA systems.

Nadezhda is designed to reduce the probability of errors at the outputs of combinational circuits due to charged particles hit. Algorithm is iterative and at each iteration it goes through 3 main stages:

The metric can be averaged logical masking, sensitive area, or even a corrected sensitive area that takes into account electrical masking of cells. The resynthesis algorithm is greedy, that is, at each iteration, it chooses the implementation of the subcircuit that has the least contribution to the sensitive area. Thus, the metric of the circuit's sensitivity to failures is guaranteed not to increase during the resynthesis process. When the algorithm reaches the limit on the number of iterations or run time, the resynthesized circuit is written to a file and verified - it is checked for equivalence with the original one.

Logical resynthesis method can be applied both at the technology-independent stage and at the post-mapping stage, when the circuit is already presented in a certain technological library. Currently, there are no methods of mapping into technology library that keep logical masking properties. Therefore, Nadezhda works with gate-level design, expressed in terms of a standard library. However, if the user has only RTL design, then we can provide preliminary synthesis in the open program Yosys. You can consider Nadezhda as a separate step in the flow, or it can be treated as one more step in the multi-step logic synthesis process.

Nadezhda can give different benefits for different circuits. It depends on the function of the device, the modes of the initial synthesis, the structure of the circuit, the settings of the algorithm and the selected constraints.

How to run

To start resynthesis run the following command:

.\src\python37-32\python.exe Nadezhda\Scripts\resynthesis_local_rewriting.pyc <input Verilog> <input Liberty> <output directory> [--iter <I>] [--step <S>] [-t <T>] [-c] [-y]
./src/miniconda3/bin/python3.8 Nadezhda/Scripts/resynthesis_local_rewriting.pyc <input Verilog> <input Liberty> <output directory> [--iter <I>] [--step <S>] [-t <T>] [-c] [-y]
Positional arguments:
1. Full path to input Verilog file
2. Full path to Liberty file with standard cell library description
3. Full path to directory for output files

Key arguments:

--iter <I>
Max number of iterations (rewrite attempts) each step

--step <S>
Number of steps

-t <T>
Timeout in seconds, 0 means no timeout

Combinational netlist flag, improves performance for combinational circuits

Yosys flag, indicates that netlist has to be mapped using Yosys before resynthesis

Working example on benchmark circuit:

.\src\python37-32\python.exe Nadezhda\Scripts\resynthesis_local_rewriting.pyc Nadezhda\Test\benchmark\c432.v  Nadezhda\Test\Nangate.lib .\results\ -y
./src/miniconda3/bin/python3.8 Nadezhda/Scripts/resynthesis_local_rewriting.pyc Nadezhda/Test/benchmark/c432.v  Nadezhda/Test/Nangate.lib ./results/ -y
You can also use example in for testing purposes:



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