Eva - Evaluation reliability tool

Quick overview

Eva - software for numerical evaluation of logic circuit reliability under the influence of single event upset (SET). The characteristics of logical masking are estimated for circuits described at the gate-level verilog netlist.

Detailed description

The fault tolerance of logic circuits is currently attracting increased interest. This is due to a number of objective reasons, including the high importance of microelectronics for fault-critical applications in the field of Space and Industry. Here is a simplified classification of destabilizing effects, as well as a classification of the errors caused by these effects. And here is another one of those objective reasons – it is a rapid increase in the soft error rate in combinational logic compared to other types of errors. It is due to the some technology trends on the soft error rate of combinational logic.

* - T. Yaran, S. Tosun Improving combinational circuit resilience against soft errors via selective resource allocation // 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

There is a large set of methods for designing around SET. In our research we deal with the most influential but probably the most underestimated technique – logic masking. It is believed that Logical masking is technology-independent and has the most impact on the soft error rate (SER) of the circuit.

* - Asadi H, Tahoori MB, Fazeli M, Miremadi SG. Efficient algorithms to accurately compute derating factors of digital circuits. Microelectron Reliab 2012;52(6):1215–26.

Actually, there are three types of Masking:

Logical masking is the most undervalued mechanism, because on the one hand it is technologically independent and has the greatest influence on the final SER, and on the other hand it is not supported by any commercially available EDA systems.

How to run

Reliability analyser computes circuit's sensitivity factor and sensitive area


.\src\python37-32\python.exe Eva\Scripts\check_reliability.pyc <input Verilog> <input Liberty> <output file>
./src/miniconda3/bin/python3.8 Eva/Scripts/check_reliability.pyc <input Verilog> <input Liberty> <output file>

Positional arguments:
1. Full path to input Verilog file (must be mapped)
2. Full path to Liberty file with standard cell library description
3. Full path to output file

Working example on benchmark circuit:

.\src\python37-32\python.exe Eva\Scripts\check_reliability.pyc Eva/Test/benchmark/c432_mapped.v  Eva/Test/Nangate.lib ./report.txt
./src/miniconda3/bin/python3.8 Eva/Scripts/check_reliability.pyc Eva/Test/benchmark/c432_mapped.v  Eva/Test/Nangate.lib ./report.txt



Please contact us with E-mail: contact@alphachip-tools.ru