Генератор Verilog описания для модулярного SAD-процессора
Выберите количество пикселей по горизонтали (от 4 до 16):
4
5
6
7
8
9
10
11
12
13
14
15
16
Выберите количество пикселей по вертикали (от 4 до 16):
4
5
6
7
8
9
10
11
12
13
14
15
16
Выберите количество бит на пиксель (от 8 до 16):
8
9
10
11
12
13
14
15
16
Использовать SSD (среднеквадратичное отклонение) вместо SAD (абсолютного среднего):
Размеры SAD: 4х4
Бит на пиксель: 8
Максимальное значение суммы: 4080
Возможный специальный базис (2
n
-1, 2
n
, 2
n
+1) но одно значение не влазит (15, 16, 17)
15*16*17 = 4080
module sad_modular_processor (pixel_a_0_0, pixel_b_0_0, pixel_a_0_1, pixel_b_0_1, pixel_a_0_2, pixel_b_0_2, pixel_a_0_3, pixel_b_0_3, pixel_a_1_0, pixel_b_1_0, pixel_a_1_1, pixel_b_1_1, pixel_a_1_2, pixel_b_1_2, pixel_a_1_3, pixel_b_1_3, pixel_a_2_0, pixel_b_2_0, pixel_a_2_1, pixel_b_2_1, pixel_a_2_2, pixel_b_2_2, pixel_a_2_3, pixel_b_2_3, pixel_a_3_0, pixel_b_3_0, pixel_a_3_1, pixel_b_3_1, pixel_a_3_2, pixel_b_3_2, pixel_a_3_3, pixel_b_3_3, out); input [7:0] pixel_a_0_0, pixel_b_0_0, pixel_a_0_1, pixel_b_0_1, pixel_a_0_2, pixel_b_0_2, pixel_a_0_3, pixel_b_0_3, pixel_a_1_0, pixel_b_1_0, pixel_a_1_1, pixel_b_1_1, pixel_a_1_2, pixel_b_1_2, pixel_a_1_3, pixel_b_1_3, pixel_a_2_0, pixel_b_2_0, pixel_a_2_1, pixel_b_2_1, pixel_a_2_2, pixel_b_2_2, pixel_a_2_3, pixel_b_2_3, pixel_a_3_0, pixel_b_3_0, pixel_a_3_1, pixel_b_3_1, pixel_a_3_2, pixel_b_3_2, pixel_a_3_3, pixel_b_3_3; wire [7:0] pixel_a_sorted_0_0, pixel_b_sorted_0_0, pixel_a_sorted_0_1, pixel_b_sorted_0_1, pixel_a_sorted_0_2, pixel_b_sorted_0_2, pixel_a_sorted_0_3, pixel_b_sorted_0_3, pixel_a_sorted_1_0, pixel_b_sorted_1_0, pixel_a_sorted_1_1, pixel_b_sorted_1_1, pixel_a_sorted_1_2, pixel_b_sorted_1_2, pixel_a_sorted_1_3, pixel_b_sorted_1_3, pixel_a_sorted_2_0, pixel_b_sorted_2_0, pixel_a_sorted_2_1, pixel_b_sorted_2_1, pixel_a_sorted_2_2, pixel_b_sorted_2_2, pixel_a_sorted_2_3, pixel_b_sorted_2_3, pixel_a_sorted_3_0, pixel_b_sorted_3_0, pixel_a_sorted_3_1, pixel_b_sorted_3_1, pixel_a_sorted_3_2, pixel_b_sorted_3_2, pixel_a_sorted_3_3, pixel_b_sorted_3_3; wire [4:0] a_17_0_0, b_17_0_0, a_17_0_1, b_17_0_1, a_17_0_2, b_17_0_2, a_17_0_3, b_17_0_3, a_17_1_0, b_17_1_0, a_17_1_1, b_17_1_1, a_17_1_2, b_17_1_2, a_17_1_3, b_17_1_3, a_17_2_0, b_17_2_0, a_17_2_1, b_17_2_1, a_17_2_2, b_17_2_2, a_17_2_3, b_17_2_3, a_17_3_0, b_17_3_0, a_17_3_1, b_17_3_1, a_17_3_2, b_17_3_2, a_17_3_3, b_17_3_3; wire [3:0] a_16_0_0, b_16_0_0, a_16_0_1, b_16_0_1, a_16_0_2, b_16_0_2, a_16_0_3, b_16_0_3, a_16_1_0, b_16_1_0, a_16_1_1, b_16_1_1, a_16_1_2, b_16_1_2, a_16_1_3, b_16_1_3, a_16_2_0, b_16_2_0, a_16_2_1, b_16_2_1, a_16_2_2, b_16_2_2, a_16_2_3, b_16_2_3, a_16_3_0, b_16_3_0, a_16_3_1, b_16_3_1, a_16_3_2, b_16_3_2, a_16_3_3, b_16_3_3; wire [3:0] a_15_0_0, b_15_0_0, a_15_0_1, b_15_0_1, a_15_0_2, b_15_0_2, a_15_0_3, b_15_0_3, a_15_1_0, b_15_1_0, a_15_1_1, b_15_1_1, a_15_1_2, b_15_1_2, a_15_1_3, b_15_1_3, a_15_2_0, b_15_2_0, a_15_2_1, b_15_2_1, a_15_2_2, b_15_2_2, a_15_2_3, b_15_2_3, a_15_3_0, b_15_3_0, a_15_3_1, b_15_3_1, a_15_3_2, b_15_3_2, a_15_3_3, b_15_3_3; wire [4:0] ch_out_17; wire [3:0] ch_out_16; wire [3:0] ch_out_15; output [11:0] out; input_sort inpsort_0_0 (pixel_a_0_0, pixel_b_0_0, pixel_a_sorted_0_0, pixel_b_sorted_0_0); input_sort inpsort_0_1 (pixel_a_0_1, pixel_b_0_1, pixel_a_sorted_0_1, pixel_b_sorted_0_1); input_sort inpsort_0_2 (pixel_a_0_2, pixel_b_0_2, pixel_a_sorted_0_2, pixel_b_sorted_0_2); input_sort inpsort_0_3 (pixel_a_0_3, pixel_b_0_3, pixel_a_sorted_0_3, pixel_b_sorted_0_3); input_sort inpsort_1_0 (pixel_a_1_0, pixel_b_1_0, pixel_a_sorted_1_0, pixel_b_sorted_1_0); input_sort inpsort_1_1 (pixel_a_1_1, pixel_b_1_1, pixel_a_sorted_1_1, pixel_b_sorted_1_1); input_sort inpsort_1_2 (pixel_a_1_2, pixel_b_1_2, pixel_a_sorted_1_2, pixel_b_sorted_1_2); input_sort inpsort_1_3 (pixel_a_1_3, pixel_b_1_3, pixel_a_sorted_1_3, pixel_b_sorted_1_3); input_sort inpsort_2_0 (pixel_a_2_0, pixel_b_2_0, pixel_a_sorted_2_0, pixel_b_sorted_2_0); input_sort inpsort_2_1 (pixel_a_2_1, pixel_b_2_1, pixel_a_sorted_2_1, pixel_b_sorted_2_1); input_sort inpsort_2_2 (pixel_a_2_2, pixel_b_2_2, pixel_a_sorted_2_2, pixel_b_sorted_2_2); input_sort inpsort_2_3 (pixel_a_2_3, pixel_b_2_3, pixel_a_sorted_2_3, pixel_b_sorted_2_3); input_sort inpsort_3_0 (pixel_a_3_0, pixel_b_3_0, pixel_a_sorted_3_0, pixel_b_sorted_3_0); input_sort inpsort_3_1 (pixel_a_3_1, pixel_b_3_1, pixel_a_sorted_3_1, pixel_b_sorted_3_1); input_sort inpsort_3_2 (pixel_a_3_2, pixel_b_3_2, pixel_a_sorted_3_2, pixel_b_sorted_3_2); input_sort inpsort_3_3 (pixel_a_3_3, pixel_b_3_3, pixel_a_sorted_3_3, pixel_b_sorted_3_3); forward_converter_17_16_15 fwd1 (pixel_a_sorted_0_0, pixel_a_sorted_0_1, pixel_a_sorted_0_2, pixel_a_sorted_0_3, pixel_a_sorted_1_0, pixel_a_sorted_1_1, pixel_a_sorted_1_2, pixel_a_sorted_1_3, pixel_a_sorted_2_0, pixel_a_sorted_2_1, pixel_a_sorted_2_2, pixel_a_sorted_2_3, pixel_a_sorted_3_0, pixel_a_sorted_3_1, pixel_a_sorted_3_2, pixel_a_sorted_3_3, a_17_0_0, a_17_0_1, a_17_0_2, a_17_0_3, a_17_1_0, a_17_1_1, a_17_1_2, a_17_1_3, a_17_2_0, a_17_2_1, a_17_2_2, a_17_2_3, a_17_3_0, a_17_3_1, a_17_3_2, a_17_3_3, a_16_0_0, a_16_0_1, a_16_0_2, a_16_0_3, a_16_1_0, a_16_1_1, a_16_1_2, a_16_1_3, a_16_2_0, a_16_2_1, a_16_2_2, a_16_2_3, a_16_3_0, a_16_3_1, a_16_3_2, a_16_3_3, a_15_0_0, a_15_0_1, a_15_0_2, a_15_0_3, a_15_1_0, a_15_1_1, a_15_1_2, a_15_1_3, a_15_2_0, a_15_2_1, a_15_2_2, a_15_2_3, a_15_3_0, a_15_3_1, a_15_3_2, a_15_3_3); forward_converter_17_16_15 fwd2 (pixel_b_sorted_0_0, pixel_b_sorted_0_1, pixel_b_sorted_0_2, pixel_b_sorted_0_3, pixel_b_sorted_1_0, pixel_b_sorted_1_1, pixel_b_sorted_1_2, pixel_b_sorted_1_3, pixel_b_sorted_2_0, pixel_b_sorted_2_1, pixel_b_sorted_2_2, pixel_b_sorted_2_3, pixel_b_sorted_3_0, pixel_b_sorted_3_1, pixel_b_sorted_3_2, pixel_b_sorted_3_3, b_17_0_0, b_17_0_1, b_17_0_2, b_17_0_3, b_17_1_0, b_17_1_1, b_17_1_2, b_17_1_3, b_17_2_0, b_17_2_1, b_17_2_2, b_17_2_3, b_17_3_0, b_17_3_1, b_17_3_2, b_17_3_3, b_16_0_0, b_16_0_1, b_16_0_2, b_16_0_3, b_16_1_0, b_16_1_1, b_16_1_2, b_16_1_3, b_16_2_0, b_16_2_1, b_16_2_2, b_16_2_3, b_16_3_0, b_16_3_1, b_16_3_2, b_16_3_3, b_15_0_0, b_15_0_1, b_15_0_2, b_15_0_3, b_15_1_0, b_15_1_1, b_15_1_2, b_15_1_3, b_15_2_0, b_15_2_1, b_15_2_2, b_15_2_3, b_15_3_0, b_15_3_1, b_15_3_2, b_15_3_3); channel_17 ch_17 (a_17_0_0, b_17_0_0, a_17_0_1, b_17_0_1, a_17_0_2, b_17_0_2, a_17_0_3, b_17_0_3, a_17_1_0, b_17_1_0, a_17_1_1, b_17_1_1, a_17_1_2, b_17_1_2, a_17_1_3, b_17_1_3, a_17_2_0, b_17_2_0, a_17_2_1, b_17_2_1, a_17_2_2, b_17_2_2, a_17_2_3, b_17_2_3, a_17_3_0, b_17_3_0, a_17_3_1, b_17_3_1, a_17_3_2, b_17_3_2, a_17_3_3, b_17_3_3, ch_out_17); channel_16 ch_16 (a_16_0_0, b_16_0_0, a_16_0_1, b_16_0_1, a_16_0_2, b_16_0_2, a_16_0_3, b_16_0_3, a_16_1_0, b_16_1_0, a_16_1_1, b_16_1_1, a_16_1_2, b_16_1_2, a_16_1_3, b_16_1_3, a_16_2_0, b_16_2_0, a_16_2_1, b_16_2_1, a_16_2_2, b_16_2_2, a_16_2_3, b_16_2_3, a_16_3_0, b_16_3_0, a_16_3_1, b_16_3_1, a_16_3_2, b_16_3_2, a_16_3_3, b_16_3_3, ch_out_16); channel_15 ch_15 (a_15_0_0, b_15_0_0, a_15_0_1, b_15_0_1, a_15_0_2, b_15_0_2, a_15_0_3, b_15_0_3, a_15_1_0, b_15_1_0, a_15_1_1, b_15_1_1, a_15_1_2, b_15_1_2, a_15_1_3, b_15_1_3, a_15_2_0, b_15_2_0, a_15_2_1, b_15_2_1, a_15_2_2, b_15_2_2, a_15_2_3, b_15_2_3, a_15_3_0, b_15_3_0, a_15_3_1, b_15_3_1, a_15_3_2, b_15_3_2, a_15_3_3, b_15_3_3, ch_out_15); reverse_converter_17_16_15 rev (ch_out_17, ch_out_16, ch_out_15, out); endmodule // make sort of inputs (first will be large than second) module input_sort(in1, in2, out1, out2); input [7:0] in1; input [7:0] in2; output reg [7:0] out1; output reg [7:0] out2; always @(*) begin if (in1 > in2) begin out1 <= in1; out2 <= in2; end else begin out1 <= in2; out2 <= in1; end end endmodule module forward_converter_17_16_15 (pixel_0_0, pixel_0_1, pixel_0_2, pixel_0_3, pixel_1_0, pixel_1_1, pixel_1_2, pixel_1_3, pixel_2_0, pixel_2_1, pixel_2_2, pixel_2_3, pixel_3_0, pixel_3_1, pixel_3_2, pixel_3_3, mod_17_0_0, mod_17_0_1, mod_17_0_2, mod_17_0_3, mod_17_1_0, mod_17_1_1, mod_17_1_2, mod_17_1_3, mod_17_2_0, mod_17_2_1, mod_17_2_2, mod_17_2_3, mod_17_3_0, mod_17_3_1, mod_17_3_2, mod_17_3_3, mod_16_0_0, mod_16_0_1, mod_16_0_2, mod_16_0_3, mod_16_1_0, mod_16_1_1, mod_16_1_2, mod_16_1_3, mod_16_2_0, mod_16_2_1, mod_16_2_2, mod_16_2_3, mod_16_3_0, mod_16_3_1, mod_16_3_2, mod_16_3_3, mod_15_0_0, mod_15_0_1, mod_15_0_2, mod_15_0_3, mod_15_1_0, mod_15_1_1, mod_15_1_2, mod_15_1_3, mod_15_2_0, mod_15_2_1, mod_15_2_2, mod_15_2_3, mod_15_3_0, mod_15_3_1, mod_15_3_2, mod_15_3_3); input [7:0] pixel_0_0, pixel_0_1, pixel_0_2, pixel_0_3, pixel_1_0, pixel_1_1, pixel_1_2, pixel_1_3, pixel_2_0, pixel_2_1, pixel_2_2, pixel_2_3, pixel_3_0, pixel_3_1, pixel_3_2, pixel_3_3; output [4:0] mod_17_0_0, mod_17_0_1, mod_17_0_2, mod_17_0_3, mod_17_1_0, mod_17_1_1, mod_17_1_2, mod_17_1_3, mod_17_2_0, mod_17_2_1, mod_17_2_2, mod_17_2_3, mod_17_3_0, mod_17_3_1, mod_17_3_2, mod_17_3_3; output [3:0] mod_16_0_0, mod_16_0_1, mod_16_0_2, mod_16_0_3, mod_16_1_0, mod_16_1_1, mod_16_1_2, mod_16_1_3, mod_16_2_0, mod_16_2_1, mod_16_2_2, mod_16_2_3, mod_16_3_0, mod_16_3_1, mod_16_3_2, mod_16_3_3; output [3:0] mod_15_0_0, mod_15_0_1, mod_15_0_2, mod_15_0_3, mod_15_1_0, mod_15_1_1, mod_15_1_2, mod_15_1_3, mod_15_2_0, mod_15_2_1, mod_15_2_2, mod_15_2_3, mod_15_3_0, mod_15_3_1, mod_15_3_2, mod_15_3_3; forward_converter fwd0_0 (pixel_0_0, mod_17_0_0, mod_16_0_0, mod_15_0_0); forward_converter fwd0_1 (pixel_0_1, mod_17_0_1, mod_16_0_1, mod_15_0_1); forward_converter fwd0_2 (pixel_0_2, mod_17_0_2, mod_16_0_2, mod_15_0_2); forward_converter fwd0_3 (pixel_0_3, mod_17_0_3, mod_16_0_3, mod_15_0_3); forward_converter fwd1_0 (pixel_1_0, mod_17_1_0, mod_16_1_0, mod_15_1_0); forward_converter fwd1_1 (pixel_1_1, mod_17_1_1, mod_16_1_1, mod_15_1_1); forward_converter fwd1_2 (pixel_1_2, mod_17_1_2, mod_16_1_2, mod_15_1_2); forward_converter fwd1_3 (pixel_1_3, mod_17_1_3, mod_16_1_3, mod_15_1_3); forward_converter fwd2_0 (pixel_2_0, mod_17_2_0, mod_16_2_0, mod_15_2_0); forward_converter fwd2_1 (pixel_2_1, mod_17_2_1, mod_16_2_1, mod_15_2_1); forward_converter fwd2_2 (pixel_2_2, mod_17_2_2, mod_16_2_2, mod_15_2_2); forward_converter fwd2_3 (pixel_2_3, mod_17_2_3, mod_16_2_3, mod_15_2_3); forward_converter fwd3_0 (pixel_3_0, mod_17_3_0, mod_16_3_0, mod_15_3_0); forward_converter fwd3_1 (pixel_3_1, mod_17_3_1, mod_16_3_1, mod_15_3_1); forward_converter fwd3_2 (pixel_3_2, mod_17_3_2, mod_16_3_2, mod_15_3_2); forward_converter fwd3_3 (pixel_3_3, mod_17_3_3, mod_16_3_3, mod_15_3_3); endmodule module forward_converter (x, x_mod17, x_mod16, x_mod15); input [7:0] x; output [4:0] x_mod17; output [3:0] x_mod16; output [3:0] x_mod15; wire [3:0] B2; wire [3:0] B3; assign B3 = x[3:0]; assign B2 = x[7:4]; assign x_mod16 = B3; mod_add #(15, 4) add1 (x_mod15, B2, B3); mod_sub #(17, 5) add2 (x_mod17, {1'b0, B2}, {1'b0, B3}); endmodule module mod_add (data_out, data_A, data_B); parameter p = 5; parameter NBRB =3; output reg [NBRB-1:0] data_out; input [NBRB-1:0] data_A, data_B; always @(data_A or data_B) begin if ({1'b0,data_A} + {1'b0,data_B} < p) data_out <= {1'b0,data_A} + {1'b0,data_B}; else data_out <= {1'b0,data_A} + {1'b0,data_B} - (p); end endmodule module mod_sub (data_out, data_A, data_B); parameter p = 5; parameter NBRB =3; output reg [NBRB-1:0] data_out; input [NBRB-1:0] data_A, data_B; always @(data_A or data_B) begin if(data_B >= data_A) data_out<= {1'b0,data_B} - {1'b0, data_A}; else data_out<= {1'b0,data_B} - {1'b0,data_A} +(p); end endmodule module channel_17 (a_17_0_0, b_17_0_0, a_17_0_1, b_17_0_1, a_17_0_2, b_17_0_2, a_17_0_3, b_17_0_3, a_17_1_0, b_17_1_0, a_17_1_1, b_17_1_1, a_17_1_2, b_17_1_2, a_17_1_3, b_17_1_3, a_17_2_0, b_17_2_0, a_17_2_1, b_17_2_1, a_17_2_2, b_17_2_2, a_17_2_3, b_17_2_3, a_17_3_0, b_17_3_0, a_17_3_1, b_17_3_1, a_17_3_2, b_17_3_2, a_17_3_3, b_17_3_3, ch_out_17); input [4:0] a_17_0_0, b_17_0_0, a_17_0_1, b_17_0_1, a_17_0_2, b_17_0_2, a_17_0_3, b_17_0_3, a_17_1_0, b_17_1_0, a_17_1_1, b_17_1_1, a_17_1_2, b_17_1_2, a_17_1_3, b_17_1_3, a_17_2_0, b_17_2_0, a_17_2_1, b_17_2_1, a_17_2_2, b_17_2_2, a_17_2_3, b_17_2_3, a_17_3_0, b_17_3_0, a_17_3_1, b_17_3_1, a_17_3_2, b_17_3_2, a_17_3_3, b_17_3_3; output [4:0] ch_out_17; wire [4:0] sub_res_0; sub_mod_17 sub0(a_17_0_0, b_17_0_0, sub_res_0); wire [4:0] sub_res_1; sub_mod_17 sub1(a_17_0_1, b_17_0_1, sub_res_1); wire [4:0] sub_res_2; sub_mod_17 sub2(a_17_0_2, b_17_0_2, sub_res_2); wire [4:0] sub_res_3; sub_mod_17 sub3(a_17_0_3, b_17_0_3, sub_res_3); wire [4:0] sub_res_4; sub_mod_17 sub4(a_17_1_0, b_17_1_0, sub_res_4); wire [4:0] sub_res_5; sub_mod_17 sub5(a_17_1_1, b_17_1_1, sub_res_5); wire [4:0] sub_res_6; sub_mod_17 sub6(a_17_1_2, b_17_1_2, sub_res_6); wire [4:0] sub_res_7; sub_mod_17 sub7(a_17_1_3, b_17_1_3, sub_res_7); wire [4:0] sub_res_8; sub_mod_17 sub8(a_17_2_0, b_17_2_0, sub_res_8); wire [4:0] sub_res_9; sub_mod_17 sub9(a_17_2_1, b_17_2_1, sub_res_9); wire [4:0] sub_res_10; sub_mod_17 sub10(a_17_2_2, b_17_2_2, sub_res_10); wire [4:0] sub_res_11; sub_mod_17 sub11(a_17_2_3, b_17_2_3, sub_res_11); wire [4:0] sub_res_12; sub_mod_17 sub12(a_17_3_0, b_17_3_0, sub_res_12); wire [4:0] sub_res_13; sub_mod_17 sub13(a_17_3_1, b_17_3_1, sub_res_13); wire [4:0] sub_res_14; sub_mod_17 sub14(a_17_3_2, b_17_3_2, sub_res_14); wire [4:0] sub_res_15; sub_mod_17 sub15(a_17_3_3, b_17_3_3, sub_res_15); wire [4:0] sum_int_level_1_num_1; sum_mod_17 sm_1_num_1(sub_res_0 , sub_res_1, sum_int_level_1_num_1); wire [4:0] sum_int_level_1_num_2; sum_mod_17 sm_1_num_2(sub_res_2 , sub_res_3, sum_int_level_1_num_2); wire [4:0] sum_int_level_1_num_3; sum_mod_17 sm_1_num_3(sub_res_4 , sub_res_5, sum_int_level_1_num_3); wire [4:0] sum_int_level_1_num_4; sum_mod_17 sm_1_num_4(sub_res_6 , sub_res_7, sum_int_level_1_num_4); wire [4:0] sum_int_level_1_num_5; sum_mod_17 sm_1_num_5(sub_res_8 , sub_res_9, sum_int_level_1_num_5); wire [4:0] sum_int_level_1_num_6; sum_mod_17 sm_1_num_6(sub_res_10 , sub_res_11, sum_int_level_1_num_6); wire [4:0] sum_int_level_1_num_7; sum_mod_17 sm_1_num_7(sub_res_12 , sub_res_13, sum_int_level_1_num_7); wire [4:0] sum_int_level_1_num_8; sum_mod_17 sm_1_num_8(sub_res_14 , sub_res_15, sum_int_level_1_num_8); wire [4:0] sum_int_level_2_num_1; sum_mod_17 sm_2_num_1(sum_int_level_1_num_1 , sum_int_level_1_num_2, sum_int_level_2_num_1); wire [4:0] sum_int_level_2_num_2; sum_mod_17 sm_2_num_2(sum_int_level_1_num_3 , sum_int_level_1_num_4, sum_int_level_2_num_2); wire [4:0] sum_int_level_2_num_3; sum_mod_17 sm_2_num_3(sum_int_level_1_num_5 , sum_int_level_1_num_6, sum_int_level_2_num_3); wire [4:0] sum_int_level_2_num_4; sum_mod_17 sm_2_num_4(sum_int_level_1_num_7 , sum_int_level_1_num_8, sum_int_level_2_num_4); wire [4:0] sum_int_level_3_num_1; sum_mod_17 sm_3_num_1(sum_int_level_2_num_1 , sum_int_level_2_num_2, sum_int_level_3_num_1); wire [4:0] sum_int_level_3_num_2; sum_mod_17 sm_3_num_2(sum_int_level_2_num_3 , sum_int_level_2_num_4, sum_int_level_3_num_2); sum_mod_17 sm_4_num_1(sum_int_level_3_num_1 , sum_int_level_3_num_2, ch_out_17); endmodule module channel_16 (a_16_0_0, b_16_0_0, a_16_0_1, b_16_0_1, a_16_0_2, b_16_0_2, a_16_0_3, b_16_0_3, a_16_1_0, b_16_1_0, a_16_1_1, b_16_1_1, a_16_1_2, b_16_1_2, a_16_1_3, b_16_1_3, a_16_2_0, b_16_2_0, a_16_2_1, b_16_2_1, a_16_2_2, b_16_2_2, a_16_2_3, b_16_2_3, a_16_3_0, b_16_3_0, a_16_3_1, b_16_3_1, a_16_3_2, b_16_3_2, a_16_3_3, b_16_3_3, ch_out_16); input [3:0] a_16_0_0, b_16_0_0, a_16_0_1, b_16_0_1, a_16_0_2, b_16_0_2, a_16_0_3, b_16_0_3, a_16_1_0, b_16_1_0, a_16_1_1, b_16_1_1, a_16_1_2, b_16_1_2, a_16_1_3, b_16_1_3, a_16_2_0, b_16_2_0, a_16_2_1, b_16_2_1, a_16_2_2, b_16_2_2, a_16_2_3, b_16_2_3, a_16_3_0, b_16_3_0, a_16_3_1, b_16_3_1, a_16_3_2, b_16_3_2, a_16_3_3, b_16_3_3; output [3:0] ch_out_16; wire [3:0] sub_res_0; sub_mod_16 sub0(a_16_0_0, b_16_0_0, sub_res_0); wire [3:0] sub_res_1; sub_mod_16 sub1(a_16_0_1, b_16_0_1, sub_res_1); wire [3:0] sub_res_2; sub_mod_16 sub2(a_16_0_2, b_16_0_2, sub_res_2); wire [3:0] sub_res_3; sub_mod_16 sub3(a_16_0_3, b_16_0_3, sub_res_3); wire [3:0] sub_res_4; sub_mod_16 sub4(a_16_1_0, b_16_1_0, sub_res_4); wire [3:0] sub_res_5; sub_mod_16 sub5(a_16_1_1, b_16_1_1, sub_res_5); wire [3:0] sub_res_6; sub_mod_16 sub6(a_16_1_2, b_16_1_2, sub_res_6); wire [3:0] sub_res_7; sub_mod_16 sub7(a_16_1_3, b_16_1_3, sub_res_7); wire [3:0] sub_res_8; sub_mod_16 sub8(a_16_2_0, b_16_2_0, sub_res_8); wire [3:0] sub_res_9; sub_mod_16 sub9(a_16_2_1, b_16_2_1, sub_res_9); wire [3:0] sub_res_10; sub_mod_16 sub10(a_16_2_2, b_16_2_2, sub_res_10); wire [3:0] sub_res_11; sub_mod_16 sub11(a_16_2_3, b_16_2_3, sub_res_11); wire [3:0] sub_res_12; sub_mod_16 sub12(a_16_3_0, b_16_3_0, sub_res_12); wire [3:0] sub_res_13; sub_mod_16 sub13(a_16_3_1, b_16_3_1, sub_res_13); wire [3:0] sub_res_14; sub_mod_16 sub14(a_16_3_2, b_16_3_2, sub_res_14); wire [3:0] sub_res_15; sub_mod_16 sub15(a_16_3_3, b_16_3_3, sub_res_15); wire [3:0] sum_int_level_1_num_1; sum_mod_16 sm_1_num_1(sub_res_0 , sub_res_1, sum_int_level_1_num_1); wire [3:0] sum_int_level_1_num_2; sum_mod_16 sm_1_num_2(sub_res_2 , sub_res_3, sum_int_level_1_num_2); wire [3:0] sum_int_level_1_num_3; sum_mod_16 sm_1_num_3(sub_res_4 , sub_res_5, sum_int_level_1_num_3); wire [3:0] sum_int_level_1_num_4; sum_mod_16 sm_1_num_4(sub_res_6 , sub_res_7, sum_int_level_1_num_4); wire [3:0] sum_int_level_1_num_5; sum_mod_16 sm_1_num_5(sub_res_8 , sub_res_9, sum_int_level_1_num_5); wire [3:0] sum_int_level_1_num_6; sum_mod_16 sm_1_num_6(sub_res_10 , sub_res_11, sum_int_level_1_num_6); wire [3:0] sum_int_level_1_num_7; sum_mod_16 sm_1_num_7(sub_res_12 , sub_res_13, sum_int_level_1_num_7); wire [3:0] sum_int_level_1_num_8; sum_mod_16 sm_1_num_8(sub_res_14 , sub_res_15, sum_int_level_1_num_8); wire [3:0] sum_int_level_2_num_1; sum_mod_16 sm_2_num_1(sum_int_level_1_num_1 , sum_int_level_1_num_2, sum_int_level_2_num_1); wire [3:0] sum_int_level_2_num_2; sum_mod_16 sm_2_num_2(sum_int_level_1_num_3 , sum_int_level_1_num_4, sum_int_level_2_num_2); wire [3:0] sum_int_level_2_num_3; sum_mod_16 sm_2_num_3(sum_int_level_1_num_5 , sum_int_level_1_num_6, sum_int_level_2_num_3); wire [3:0] sum_int_level_2_num_4; sum_mod_16 sm_2_num_4(sum_int_level_1_num_7 , sum_int_level_1_num_8, sum_int_level_2_num_4); wire [3:0] sum_int_level_3_num_1; sum_mod_16 sm_3_num_1(sum_int_level_2_num_1 , sum_int_level_2_num_2, sum_int_level_3_num_1); wire [3:0] sum_int_level_3_num_2; sum_mod_16 sm_3_num_2(sum_int_level_2_num_3 , sum_int_level_2_num_4, sum_int_level_3_num_2); sum_mod_16 sm_4_num_1(sum_int_level_3_num_1 , sum_int_level_3_num_2, ch_out_16); endmodule module channel_15 (a_15_0_0, b_15_0_0, a_15_0_1, b_15_0_1, a_15_0_2, b_15_0_2, a_15_0_3, b_15_0_3, a_15_1_0, b_15_1_0, a_15_1_1, b_15_1_1, a_15_1_2, b_15_1_2, a_15_1_3, b_15_1_3, a_15_2_0, b_15_2_0, a_15_2_1, b_15_2_1, a_15_2_2, b_15_2_2, a_15_2_3, b_15_2_3, a_15_3_0, b_15_3_0, a_15_3_1, b_15_3_1, a_15_3_2, b_15_3_2, a_15_3_3, b_15_3_3, ch_out_15); input [3:0] a_15_0_0, b_15_0_0, a_15_0_1, b_15_0_1, a_15_0_2, b_15_0_2, a_15_0_3, b_15_0_3, a_15_1_0, b_15_1_0, a_15_1_1, b_15_1_1, a_15_1_2, b_15_1_2, a_15_1_3, b_15_1_3, a_15_2_0, b_15_2_0, a_15_2_1, b_15_2_1, a_15_2_2, b_15_2_2, a_15_2_3, b_15_2_3, a_15_3_0, b_15_3_0, a_15_3_1, b_15_3_1, a_15_3_2, b_15_3_2, a_15_3_3, b_15_3_3; output [3:0] ch_out_15; wire [3:0] sub_res_0; sub_mod_15 sub0(a_15_0_0, b_15_0_0, sub_res_0); wire [3:0] sub_res_1; sub_mod_15 sub1(a_15_0_1, b_15_0_1, sub_res_1); wire [3:0] sub_res_2; sub_mod_15 sub2(a_15_0_2, b_15_0_2, sub_res_2); wire [3:0] sub_res_3; sub_mod_15 sub3(a_15_0_3, b_15_0_3, sub_res_3); wire [3:0] sub_res_4; sub_mod_15 sub4(a_15_1_0, b_15_1_0, sub_res_4); wire [3:0] sub_res_5; sub_mod_15 sub5(a_15_1_1, b_15_1_1, sub_res_5); wire [3:0] sub_res_6; sub_mod_15 sub6(a_15_1_2, b_15_1_2, sub_res_6); wire [3:0] sub_res_7; sub_mod_15 sub7(a_15_1_3, b_15_1_3, sub_res_7); wire [3:0] sub_res_8; sub_mod_15 sub8(a_15_2_0, b_15_2_0, sub_res_8); wire [3:0] sub_res_9; sub_mod_15 sub9(a_15_2_1, b_15_2_1, sub_res_9); wire [3:0] sub_res_10; sub_mod_15 sub10(a_15_2_2, b_15_2_2, sub_res_10); wire [3:0] sub_res_11; sub_mod_15 sub11(a_15_2_3, b_15_2_3, sub_res_11); wire [3:0] sub_res_12; sub_mod_15 sub12(a_15_3_0, b_15_3_0, sub_res_12); wire [3:0] sub_res_13; sub_mod_15 sub13(a_15_3_1, b_15_3_1, sub_res_13); wire [3:0] sub_res_14; sub_mod_15 sub14(a_15_3_2, b_15_3_2, sub_res_14); wire [3:0] sub_res_15; sub_mod_15 sub15(a_15_3_3, b_15_3_3, sub_res_15); wire [3:0] sum_int_level_1_num_1; sum_mod_15 sm_1_num_1(sub_res_0 , sub_res_1, sum_int_level_1_num_1); wire [3:0] sum_int_level_1_num_2; sum_mod_15 sm_1_num_2(sub_res_2 , sub_res_3, sum_int_level_1_num_2); wire [3:0] sum_int_level_1_num_3; sum_mod_15 sm_1_num_3(sub_res_4 , sub_res_5, sum_int_level_1_num_3); wire [3:0] sum_int_level_1_num_4; sum_mod_15 sm_1_num_4(sub_res_6 , sub_res_7, sum_int_level_1_num_4); wire [3:0] sum_int_level_1_num_5; sum_mod_15 sm_1_num_5(sub_res_8 , sub_res_9, sum_int_level_1_num_5); wire [3:0] sum_int_level_1_num_6; sum_mod_15 sm_1_num_6(sub_res_10 , sub_res_11, sum_int_level_1_num_6); wire [3:0] sum_int_level_1_num_7; sum_mod_15 sm_1_num_7(sub_res_12 , sub_res_13, sum_int_level_1_num_7); wire [3:0] sum_int_level_1_num_8; sum_mod_15 sm_1_num_8(sub_res_14 , sub_res_15, sum_int_level_1_num_8); wire [3:0] sum_int_level_2_num_1; sum_mod_15 sm_2_num_1(sum_int_level_1_num_1 , sum_int_level_1_num_2, sum_int_level_2_num_1); wire [3:0] sum_int_level_2_num_2; sum_mod_15 sm_2_num_2(sum_int_level_1_num_3 , sum_int_level_1_num_4, sum_int_level_2_num_2); wire [3:0] sum_int_level_2_num_3; sum_mod_15 sm_2_num_3(sum_int_level_1_num_5 , sum_int_level_1_num_6, sum_int_level_2_num_3); wire [3:0] sum_int_level_2_num_4; sum_mod_15 sm_2_num_4(sum_int_level_1_num_7 , sum_int_level_1_num_8, sum_int_level_2_num_4); wire [3:0] sum_int_level_3_num_1; sum_mod_15 sm_3_num_1(sum_int_level_2_num_1 , sum_int_level_2_num_2, sum_int_level_3_num_1); wire [3:0] sum_int_level_3_num_2; sum_mod_15 sm_3_num_2(sum_int_level_2_num_3 , sum_int_level_2_num_4, sum_int_level_3_num_2); sum_mod_15 sm_4_num_1(sum_int_level_3_num_1 , sum_int_level_3_num_2, ch_out_15); endmodule module sub_mod_17 (in1, in2, out); input [4:0] in1, in2; output [4:0] out; wire [5:0] data; assign data = 17 + in1 - in2; mod_17_33 mdval(data, out); endmodule module mod_17_33 (in, out); input [5:0] in; output reg [4:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; 9: out = 9; 10: out = 10; 11: out = 11; 12: out = 12; 13: out = 13; 14: out = 14; 15: out = 15; 16: out = 16; 17: out = 0; 18: out = 1; 19: out = 2; 20: out = 3; 21: out = 4; 22: out = 5; 23: out = 6; 24: out = 7; 25: out = 8; 26: out = 9; 27: out = 10; 28: out = 11; 29: out = 12; 30: out = 13; 31: out = 14; 32: out = 15; 33: out = 16; default: out = 0; endcase end endmodule module sub_mod_16 (in1, in2, out); input [3:0] in1, in2; output [3:0] out; wire [4:0] data; assign data = 16 + in1 - in2; assign out = data[3:0]; endmodule module sub_mod_15 (in1, in2, out); input [3:0] in1, in2; output [3:0] out; wire [4:0] data; assign data = 15 + in1 - in2; mod_15_29 mdval(data, out); endmodule module mod_15_29 (in, out); input [4:0] in; output reg [3:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; 9: out = 9; 10: out = 10; 11: out = 11; 12: out = 12; 13: out = 13; 14: out = 14; 15: out = 0; 16: out = 1; 17: out = 2; 18: out = 3; 19: out = 4; 20: out = 5; 21: out = 6; 22: out = 7; 23: out = 8; 24: out = 9; 25: out = 10; 26: out = 11; 27: out = 12; 28: out = 13; 29: out = 14; default: out = 0; endcase end endmodule module sum_mod_17 (in1, in2, out); input [4:0] in1, in2; output [4:0] out; wire [5:0] data; assign data = in1 + in2; mod_17_32 mdval(data, out); endmodule module mod_17_32 (in, out); input [5:0] in; output reg [4:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; 9: out = 9; 10: out = 10; 11: out = 11; 12: out = 12; 13: out = 13; 14: out = 14; 15: out = 15; 16: out = 16; 17: out = 0; 18: out = 1; 19: out = 2; 20: out = 3; 21: out = 4; 22: out = 5; 23: out = 6; 24: out = 7; 25: out = 8; 26: out = 9; 27: out = 10; 28: out = 11; 29: out = 12; 30: out = 13; 31: out = 14; 32: out = 15; default: out = 0; endcase end endmodule module sum_mod_16 (in1, in2, out); input [3:0] in1, in2; output [3:0] out; wire [4:0] data; assign data = in1 + in2; assign out = data[3:0]; endmodule // Sum modulo (2^4 - 1) = 15 module sum_mod_15 (A, B, S); input [3:0] A; input [3:0] B; output[3:0] S; wire [3:0] G; wire [3:0] P; wire [3:0] C; assign G[0] = A[0]&B[0]; assign G[1] = A[1]&B[1]; assign G[2] = A[2]&B[2]; assign G[3] = A[3]&B[3]; assign P[0] = A[0]^B[0]; assign P[1] = A[1]^B[1]; assign P[2] = A[2]^B[2]; assign P[3] = A[3]^B[3]; assign C[0] = G[0] | G[3]&P[0] | G[2]&P[0]&P[3] | G[1]&P[0]&P[3]&P[2]; assign C[1] = G[1] | G[0]&P[1] | G[3]&P[1]&P[0] | G[2]&P[1]&P[0]&P[3]; assign C[2] = G[2] | G[1]&P[2] | G[0]&P[2]&P[1] | G[3]&P[2]&P[1]&P[0]; assign C[3] = G[3] | G[2]&P[3] | G[1]&P[3]&P[2] | G[0]&P[3]&P[2]&P[1]; assign S[0] = (P[0]&&(~P[3:0]))^C[3]; assign S[1] = (P[1]&&(~P[3:0]))^C[0]; assign S[2] = (P[2]&&(~P[3:0]))^C[1]; assign S[3] = (P[3]&&(~P[3:0]))^C[2]; endmodule module reverse_converter_17_16_15 (x1, x2, x3, out); input [4:0] x1; input [3:0] x2; input [3:0] x3; wire [7:0] a1; wire [7:0] a2; wire [7:0] a3; wire [7:0] sum1; wire [7:0] sum2; wire [7:0] sum3; output [11:0] out; coef_a1 ca1(x1,a1); coef_a2 ca2(x2,a2); coef_a3 ca3(x3,a3); sum_mod_255 sm1(a2, a3, sum1); sub_a1_x1 sm2(a1, x1, sum2); sum_mod_255 sm3(sum1, sum2, sum3); assign out[0] = x2[0]; assign out[1] = x2[1]; assign out[2] = x2[2]; assign out[3] = x2[3]; assign out[4] = sum3[0]; assign out[5] = sum3[1]; assign out[6] = sum3[2]; assign out[7] = sum3[3]; assign out[8] = sum3[4]; assign out[9] = sum3[5]; assign out[10] = sum3[6]; assign out[11] = sum3[7]; endmodule module coef_a3 (x3, a3); input [3:0] x3; output [7:0] a3; assign a3[7] = x3[0]; assign a3[6] = x3[3]; assign a3[5] = x3[2]; assign a3[4] = x3[1]; assign a3[3] = x3[0]; assign a3[2] = x3[3]; assign a3[1] = x3[2]; assign a3[0] = x3[1]; endmodule module coef_a2 (x2, a2); input [3:0] x2; output [7:0] a2; assign a2[7] = ~x2[3]; assign a2[6] = ~x2[2]; assign a2[5] = ~x2[1]; assign a2[4] = ~x2[0]; assign a2[3] = 1; assign a2[2] = 1; assign a2[1] = 1; assign a2[0] = 1; endmodule module coef_a1 (x1, a1); input [4:0] x1; output [7:0] a1; wire bx; assign bx = x1[4] ^ x1[0]; assign a1[7] = bx; assign a1[6] = x1[3]; assign a1[5] = x1[2]; assign a1[4] = x1[1]; assign a1[3] = bx; assign a1[2] = x1[3]; assign a1[1] = x1[2]; assign a1[0] = x1[1]; endmodule module sub_a1_x1 (a1, x1, out); input [7:0] a1; input [4:0] x1; output [7:0] out; assign out = a1 - x1; endmodule // Sum modulo (2^8 - 1) = 255 module sum_mod_255 (A, B, S); input [7:0] A; input [7:0] B; output[7:0] S; wire [7:0] G; wire [7:0] P; wire [7:0] C; assign G[0] = A[0]&B[0]; assign G[1] = A[1]&B[1]; assign G[2] = A[2]&B[2]; assign G[3] = A[3]&B[3]; assign G[4] = A[4]&B[4]; assign G[5] = A[5]&B[5]; assign G[6] = A[6]&B[6]; assign G[7] = A[7]&B[7]; assign P[0] = A[0]^B[0]; assign P[1] = A[1]^B[1]; assign P[2] = A[2]^B[2]; assign P[3] = A[3]^B[3]; assign P[4] = A[4]^B[4]; assign P[5] = A[5]^B[5]; assign P[6] = A[6]^B[6]; assign P[7] = A[7]^B[7]; assign C[0] = G[0] | G[7]&P[0] | G[6]&P[0]&P[7] | G[5]&P[0]&P[7]&P[6] | G[4]&P[0]&P[7]&P[6]&P[5] | G[3]&P[0]&P[7]&P[6]&P[5]&P[4] | G[2]&P[0]&P[7]&P[6]&P[5]&P[4]&P[3] | G[1]&P[0]&P[7]&P[6]&P[5]&P[4]&P[3]&P[2]; assign C[1] = G[1] | G[0]&P[1] | G[7]&P[1]&P[0] | G[6]&P[1]&P[0]&P[7] | G[5]&P[1]&P[0]&P[7]&P[6] | G[4]&P[1]&P[0]&P[7]&P[6]&P[5] | G[3]&P[1]&P[0]&P[7]&P[6]&P[5]&P[4] | G[2]&P[1]&P[0]&P[7]&P[6]&P[5]&P[4]&P[3]; assign C[2] = G[2] | G[1]&P[2] | G[0]&P[2]&P[1] | G[7]&P[2]&P[1]&P[0] | G[6]&P[2]&P[1]&P[0]&P[7] | G[5]&P[2]&P[1]&P[0]&P[7]&P[6] | G[4]&P[2]&P[1]&P[0]&P[7]&P[6]&P[5] | G[3]&P[2]&P[1]&P[0]&P[7]&P[6]&P[5]&P[4]; assign C[3] = G[3] | G[2]&P[3] | G[1]&P[3]&P[2] | G[0]&P[3]&P[2]&P[1] | G[7]&P[3]&P[2]&P[1]&P[0] | G[6]&P[3]&P[2]&P[1]&P[0]&P[7] | G[5]&P[3]&P[2]&P[1]&P[0]&P[7]&P[6] | G[4]&P[3]&P[2]&P[1]&P[0]&P[7]&P[6]&P[5]; assign C[4] = G[4] | G[3]&P[4] | G[2]&P[4]&P[3] | G[1]&P[4]&P[3]&P[2] | G[0]&P[4]&P[3]&P[2]&P[1] | G[7]&P[4]&P[3]&P[2]&P[1]&P[0] | G[6]&P[4]&P[3]&P[2]&P[1]&P[0]&P[7] | G[5]&P[4]&P[3]&P[2]&P[1]&P[0]&P[7]&P[6]; assign C[5] = G[5] | G[4]&P[5] | G[3]&P[5]&P[4] | G[2]&P[5]&P[4]&P[3] | G[1]&P[5]&P[4]&P[3]&P[2] | G[0]&P[5]&P[4]&P[3]&P[2]&P[1] | G[7]&P[5]&P[4]&P[3]&P[2]&P[1]&P[0] | G[6]&P[5]&P[4]&P[3]&P[2]&P[1]&P[0]&P[7]; assign C[6] = G[6] | G[5]&P[6] | G[4]&P[6]&P[5] | G[3]&P[6]&P[5]&P[4] | G[2]&P[6]&P[5]&P[4]&P[3] | G[1]&P[6]&P[5]&P[4]&P[3]&P[2] | G[0]&P[6]&P[5]&P[4]&P[3]&P[2]&P[1] | G[7]&P[6]&P[5]&P[4]&P[3]&P[2]&P[1]&P[0]; assign C[7] = G[7] | G[6]&P[7] | G[5]&P[7]&P[6] | G[4]&P[7]&P[6]&P[5] | G[3]&P[7]&P[6]&P[5]&P[4] | G[2]&P[7]&P[6]&P[5]&P[4]&P[3] | G[1]&P[7]&P[6]&P[5]&P[4]&P[3]&P[2] | G[0]&P[7]&P[6]&P[5]&P[4]&P[3]&P[2]&P[1]; assign S[0] = (P[0]&&(~P[7:0]))^C[7]; assign S[1] = (P[1]&&(~P[7:0]))^C[0]; assign S[2] = (P[2]&&(~P[7:0]))^C[1]; assign S[3] = (P[3]&&(~P[7:0]))^C[2]; assign S[4] = (P[4]&&(~P[7:0]))^C[3]; assign S[5] = (P[5]&&(~P[7:0]))^C[4]; assign S[6] = (P[6]&&(~P[7:0]))^C[5]; assign S[7] = (P[7]&&(~P[7:0]))^C[6]; endmodule module atest_bench(); reg [7:0] pixel_a_0_0; reg [7:0] pixel_b_0_0; reg [7:0] pixel_a_0_1; reg [7:0] pixel_b_0_1; reg [7:0] pixel_a_0_2; reg [7:0] pixel_b_0_2; reg [7:0] pixel_a_0_3; reg [7:0] pixel_b_0_3; reg [7:0] pixel_a_1_0; reg [7:0] pixel_b_1_0; reg [7:0] pixel_a_1_1; reg [7:0] pixel_b_1_1; reg [7:0] pixel_a_1_2; reg [7:0] pixel_b_1_2; reg [7:0] pixel_a_1_3; reg [7:0] pixel_b_1_3; reg [7:0] pixel_a_2_0; reg [7:0] pixel_b_2_0; reg [7:0] pixel_a_2_1; reg [7:0] pixel_b_2_1; reg [7:0] pixel_a_2_2; reg [7:0] pixel_b_2_2; reg [7:0] pixel_a_2_3; reg [7:0] pixel_b_2_3; reg [7:0] pixel_a_3_0; reg [7:0] pixel_b_3_0; reg [7:0] pixel_a_3_1; reg [7:0] pixel_b_3_1; reg [7:0] pixel_a_3_2; reg [7:0] pixel_b_3_2; reg [7:0] pixel_a_3_3; reg [7:0] pixel_b_3_3; wire [11:0] out; integer i, j, l, m, t; reg dummy; wire complete; integer fori; sad_modular_processor r1 (pixel_a_0_0, pixel_b_0_0, pixel_a_0_1, pixel_b_0_1, pixel_a_0_2, pixel_b_0_2, pixel_a_0_3, pixel_b_0_3, pixel_a_1_0, pixel_b_1_0, pixel_a_1_1, pixel_b_1_1, pixel_a_1_2, pixel_b_1_2, pixel_a_1_3, pixel_b_1_3, pixel_a_2_0, pixel_b_2_0, pixel_a_2_1, pixel_b_2_1, pixel_a_2_2, pixel_b_2_2, pixel_a_2_3, pixel_b_2_3, pixel_a_3_0, pixel_b_3_0, pixel_a_3_1, pixel_b_3_1, pixel_a_3_2, pixel_b_3_2, pixel_a_3_3, pixel_b_3_3, out); initial begin pixel_a_0_0 = 207; pixel_b_0_0 = 209; pixel_a_0_1 = 121; pixel_b_0_1 = 188; pixel_a_0_2 = 91; pixel_b_0_2 = 235; pixel_a_0_3 = 12; pixel_b_0_3 = 186; pixel_a_1_0 = 61; pixel_b_1_0 = 142; pixel_a_1_1 = 126; pixel_b_1_1 = 163; pixel_a_1_2 = 33; pixel_b_1_2 = 128; pixel_a_1_3 = 214; pixel_b_1_3 = 108; pixel_a_2_0 = 166; pixel_b_2_0 = 11; pixel_a_2_1 = 105; pixel_b_2_1 = 45; pixel_a_2_2 = 68; pixel_b_2_2 = 244; pixel_a_2_3 = 242; pixel_b_2_3 = 89; pixel_a_3_0 = 5; pixel_b_3_0 = 161; pixel_a_3_1 = 73; pixel_b_3_1 = 95; pixel_a_3_2 = 252; pixel_b_3_2 = 136; pixel_a_3_3 = 213; pixel_b_3_3 = 203; #1 dummy = 1; fori = 1554; $display ("!!! Res=(%d) Expect=(%d)", out, fori); l = out; if (l != fori) begin $display ("!!! Error (%d, %d)!!!", fori, l); end #1 dummy = 1; pixel_a_0_0 = 89; pixel_b_0_0 = 78; pixel_a_0_1 = 135; pixel_b_0_1 = 180; pixel_a_0_2 = 58; pixel_b_0_2 = 147; pixel_a_0_3 = 110; pixel_b_0_3 = 119; pixel_a_1_0 = 33; pixel_b_1_0 = 236; pixel_a_1_1 = 26; pixel_b_1_1 = 67; pixel_a_1_2 = 108; pixel_b_1_2 = 240; pixel_a_1_3 = 175; pixel_b_1_3 = 19; pixel_a_2_0 = 252; pixel_b_2_0 = 24; pixel_a_2_1 = 64; pixel_b_2_1 = 64; pixel_a_2_2 = 12; pixel_b_2_2 = 50; pixel_a_2_3 = 153; pixel_b_2_3 = 18; pixel_a_3_0 = 212; pixel_b_3_0 = 226; pixel_a_3_1 = 113; pixel_b_3_1 = 208; pixel_a_3_2 = 106; pixel_b_3_2 = 70; pixel_a_3_3 = 155; pixel_b_3_3 = 195; #1 dummy = 1; fori = 1272; $display ("!!! Res=(%d) Expect=(%d)", out, fori); l = out; if (l != fori) begin $display ("!!! Error (%d, %d)!!!", fori, l); end #1 dummy = 1; // Special case: minimum pixel_a_0_0 = 149; pixel_b_0_0 = 149; pixel_a_0_1 = 35; pixel_b_0_1 = 35; pixel_a_0_2 = 119; pixel_b_0_2 = 119; pixel_a_0_3 = 207; pixel_b_0_3 = 207; pixel_a_1_0 = 182; pixel_b_1_0 = 182; pixel_a_1_1 = 230; pixel_b_1_1 = 230; pixel_a_1_2 = 70; pixel_b_1_2 = 70; pixel_a_1_3 = 216; pixel_b_1_3 = 216; pixel_a_2_0 = 210; pixel_b_2_0 = 210; pixel_a_2_1 = 97; pixel_b_2_1 = 97; pixel_a_2_2 = 27; pixel_b_2_2 = 27; pixel_a_2_3 = 63; pixel_b_2_3 = 63; pixel_a_3_0 = 81; pixel_b_3_0 = 81; pixel_a_3_1 = 202; pixel_b_3_1 = 202; pixel_a_3_2 = 82; pixel_b_3_2 = 82; pixel_a_3_3 = 77; pixel_b_3_3 = 77; #1 dummy = 1; fori = 0; $display ("!!! Res=(%d) Expect=(%d)", out, fori); l = out; if (l != fori) begin $display ("!!! Error (%d, %d)!!!", fori, l); end #1 dummy = 1; // Special case: maximum pixel_a_0_0 = 0; pixel_b_0_0 = 255; pixel_a_0_1 = 0; pixel_b_0_1 = 255; pixel_a_0_2 = 255; pixel_b_0_2 = 0; pixel_a_0_3 = 0; pixel_b_0_3 = 255; pixel_a_1_0 = 0; pixel_b_1_0 = 255; pixel_a_1_1 = 0; pixel_b_1_1 = 255; pixel_a_1_2 = 0; pixel_b_1_2 = 255; pixel_a_1_3 = 0; pixel_b_1_3 = 255; pixel_a_2_0 = 255; pixel_b_2_0 = 0; pixel_a_2_1 = 0; pixel_b_2_1 = 255; pixel_a_2_2 = 0; pixel_b_2_2 = 255; pixel_a_2_3 = 255; pixel_b_2_3 = 0; pixel_a_3_0 = 0; pixel_b_3_0 = 255; pixel_a_3_1 = 0; pixel_b_3_1 = 255; pixel_a_3_2 = 255; pixel_b_3_2 = 0; pixel_a_3_3 = 255; pixel_b_3_3 = 0; #1 dummy = 1; fori = 4080; $display ("!!! Res=(%d) Expect=(%d)", out, fori); l = out; if (l != fori) begin $display ("!!! Error (%d, %d)!!!", fori, l); end #1 dummy = 1; end endmodule
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