Генератор Verilog для индексных умножителей по модулю

Выберите модуль (от 3 до 1000):

Тип умножителя:

Использовать case в таблице преобразования:

Первообразный корень для 7 = 3
Число P-1 может быть разложено на 2 взаимно простых множителя: 6 = 2*3
Таблица преобразования [Подробности]:

1	2	3	4	5	6
0	2	1	4	5	3
( 0 0 )	( 0 2 )	( 1 1 )	( 0 1 )	( 1 2 )	( 1 0 )

module multiplication_mod_7(inp1, inp2, out);
	input [2:0] inp1;
	input [2:0] inp2;
	output [2:0] out;
	wire [2:0] out_pre;
	wire [1:0] w_1_0;
	wire [1:0] w_2_0;
	wire [1:0] wout_0;
	wire [1:0] w_1_1;
	wire [1:0] w_2_1;
	wire [1:0] wout_1;
	lut_input_7 lut1(inp1, w_1_0, w_1_1);
	lut_input_7 lut2(inp2, w_2_0, w_2_1);
	sum_modulo_2 sm0(w_1_0, w_2_0, wout_0);
	sum_modulo_3 sm1(w_1_1, w_2_1, wout_1);
	lut_output_7 lut3(wout_0, wout_1, out_pre);
	singularity_pass sp (inp1, inp2, out_pre, out);
endmodule

module singularity_pass (inp1, inp2, real_out, out);
	input [2:0] inp1;
	input [2:0] inp2;
	input [2:0] real_out;
	output reg [2:0] out;
	
	always @ (*)
	begin
		if (inp1 == 0 || inp2 == 0)
		begin
			out <= 0;
		end
		else
		begin
			out <= real_out;
		end
	end
endmodule

module sum_modulo_2(inp1, inp2, out);
	input [1:0] inp1;
	input [1:0] inp2;
	output reg [1:0] out;
	wire [2:0] int;
	assign int = inp1 + inp2;
	always @ (*)
	begin
		if (int < 2)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 2;
		end
	end
endmodule

module sum_modulo_3(inp1, inp2, out);
	input [1:0] inp1;
	input [1:0] inp2;
	output reg [1:0] out;
	wire [2:0] int;
	assign int = inp1 + inp2;
	always @ (*)
	begin
		if (int < 3)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 3;
		end
	end
endmodule

module lut_output_7(inp0, inp1, out);
	output reg [2:0] out;
	input [1:0] inp0;
	input [1:0] inp1;
	wire [3:0] inp;
	assign inp = {inp0[1:0], inp1[1:0]};
	always @ (*)
	begin
	case(inp)
		{2'd0, 2'd0}: out <= 1;
		{2'd0, 2'd2}: out <= 2;
		{2'd1, 2'd1}: out <= 3;
		{2'd0, 2'd1}: out <= 4;
		{2'd1, 2'd2}: out <= 5;
		{2'd1, 2'd0}: out <= 6;
		default: out <= 0;
	endcase
	end
endmodule

module lut_input_7(inp, out0, out1);
	input [2:0] inp;
	output reg [1:0] out0;
	output reg [1:0] out1;
	always @ (inp)
	begin
		case(inp)
		1: begin
			out0 <= 0;
			out1 <= 0;
		end
		2: begin
			out0 <= 0;
			out1 <= 2;
		end
		3: begin
			out0 <= 1;
			out1 <= 1;
		end
		4: begin
			out0 <= 0;
			out1 <= 1;
		end
		5: begin
			out0 <= 1;
			out1 <= 2;
		end
		6: begin
			out0 <= 1;
			out1 <= 0;
		end
		default:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		endcase
	end
endmodule

module atop_testbench();
	reg [2:0] inp1;
	reg [2:0] inp2;
	wire [2:0] out;

integer i, j, l, m, k, t;
	reg dummy;
	integer fori, forj;
	multiplication_mod_7 mul1(inp1, inp2, out);
	initial
	begin
	k = 1;
	for (fori = 0; fori < 7; fori = fori + 1)
	begin
	for (forj = 0; forj < 7; forj = forj + 1)
	begin
		inp1 = fori;
		inp2 = forj;
		#1 dummy = 1;
		i = (fori*forj)%7;
		$display ("!!! OP1 = (%d) OP2 = (%d) RES = (%d) EXPECT = (%d)", fori, forj, out, i);
		l = out;
		if (l != i)
		begin
			$display ("!!! Error (%d, %d)!!!", i, l);
		end
		#1 dummy = 1;
	end
	end
	end
endmodule

	1	0 0
	2	0 2
	3	1 1
	4	0 1
	5	1 2
	6	1 0

Сумматор
по
модулю 2

(1 + 0) mod 2 = 1

Сумматор
по
модулю 3

(0 + 2) mod 3 = 2

0 0	1
0 1	4
0 2	2
1 0	6
1 1	3
1 2	5

	1	0 0
	2	0 2
	3	1 1
	4	0 1
	5	1 2
	6	1 0